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dc.contributor.authorAustin, Todd M.en_US
dc.contributor.authorSohi, Gurindar Singhen_US
dc.date.accessioned2007-07-13T19:18:46Z
dc.date.available2007-07-13T19:18:46Z
dc.date.issued1996en_US
dc.identifier.citationAustin, T.M., & Sohi, G.S. (1996). High-bandwidth address translation for multiple-issue processors. In ISCA '96: The 23rd Annual International Conference on Computer Architecture, 22-24 May 1996, 24 (2), 158-67.en_US
dc.identifier.urihttp://digital.library.wisc.edu/1793/9182
dc.descriptionThis material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.en_US
dc.format.extent1556912 bytes
dc.format.mimetypeapplication/pdfen_US
dc.format.mimetypeapplication/pdf
dc.publisherACMen_US
dc.relation.ispartofhttp://www.ieee.org/en_US
dc.relation.ispartofhttp://portal.acm.org/browse_dl.cfm?coll=ACM&dl=ACM&idx=J89&linked=1&part=newsletteren_US
dc.rightsCopyright 1996 Institute of Electrical and Electronics Engineersen_US
dc.rights©20xx IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.en_US
dc.titleHigh-bandwidth address translation for multiple-issue processorsen_US
dc.typeArticle
dc.identifier.doihttp://dx.doi.org/10.1145/232974.232990en_US


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