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    • College of Letters and Science, University of Wisconsin–Madison
    • Department of Computer Sciences, UW-Madison
    • CS Technical Reports
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    Cache Power Budgeting for Performance

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    File(s)
    TR1791 (978.7Kb)
    Date
    2013-04-26
    Author
    Sen, Rathijit
    Wood, David A.
    Publisher
    University of Wisconsin-Madison Department of Computer Sciences
    Metadata
    Show full item record
    Abstract
    Power is arguably the critical resource in computer system design today. In this work, we focus on maximizing performance of a chip multiprocessor (CMP) system, for a given power budget, by developing techniques to budget power between processor cores and caches. Dynamic cache configuration can reduce cache capacity and associativity, thereby freeing up chip power, but may increase the miss rate (and potentially memory power). Dynamic voltage and frequency scaling (DVFS) can exploit the saved power to increase core performance, potentially increasing system performance. Detailed simulation models show that carefully budgeting power between cores and caches can improve system performance 2-16% for 11 of 17 workloads. To intelligently budget power between cores and caches, we investigate using hardware support to drive analytical models of system power and performance. Online estimation enables real-time feedback and adaptation to dynamic changes such as operating system interactions or changing workload mixes. We demonstrate an integrated online framework that combines a cache reuse model, performance model, power model and DVFS model to identify optimal power-budgeted configurations.
    Subject
    DVFS
    Stack Distance
    Reuse Distance
    World Set
    Power Budget
    LLC
    Cache
    PLRU
    Static Power
    Permanent Link
    http://digital.library.wisc.edu/1793/65385
    Citation
    TR1791
    Part of
    • CS Technical Reports

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