Now showing items 1-5 of 5

    • Reducing Coherence Overheads with Multi-line Invalidation (MLI) Messages 

      Yoon, Hongil; Sohi, Gurindar (2013-05-31)
      Most multiprocessors employ coherent caches despite the overheads of doing so. As future processors will be multi-processors with elaborate cache hierarchies, the overheads of cache coherence will be an important area for ...
    • Reducing GPU Address Translation Overhead with Virtual Caching 

      Yoon, Hongil; Lowe-Power, Jason; Sohi, Gurindar S. (2016-12-05)
      Heterogeneous computing on tightly-integrated CPU-GPU systems is ubiquitous, and to increase programmability, many of these systems support virtual address accesses from GPU hardware. However, there is no free lunch. ...
    • Region-level Tracking for Scalable Directory Cache 

      Yoon, Hongil; Sohi, Gurindar S. (2015-04-19)
      Traditional coherence directories track sharing information at a cache-line granularity. In practice, however, as data sharing occurs at a coarser granularity in a large region of memory, common sharing patterns tend to ...
    • Revisiting Virtual L1 Caches: A Practical Design Using Dynamic Synonym Remapping 

      Yoon, Hongil; Sohi, Gurindar (2015-10-27)
      Virtual caches have potentially lower access latency and energy consumption than physical caches due not to consulting the TLB prior to every cache access. However, they have not been popular in commercial designs. The ...
    • SIP: Speculative Insertion Policy for High Performance Caching 

      Yoon, Hongil; Zhang, Tan; H.Lipasti, Mikko (University of Wisconsin-Madison Department of Computer Sciences, 2010)
      High performance cache mechanisms have a great impact on overall performance of computer systems by reducing memory-access latency. Least-Recently Used (LRU) mecha- nism can achieve good performance in small workload; how- ...