An Analysis of FPGA-based Architectures and Algorithm Implementations for the Compact Muon Solenoid Experiment Regional Calorimeter Trigger Phase-I Luminosity Upgrade

Abstract

The Large Hadron Collider's (LHC) Compact Muon Solenoid (CMS) is a high-energy physics experiment designed to observe and analyze particle collisions at a rate of one billion collisions per second. The CMS experiment relies on a high-performance system of custom processing elements (collectively known as the CMS Trigger) to perform real-time pre-processing of collision data and select the most interesting data for further study. Portions of the CMS Trigger are due to be upgraded in several phases over the next ten years to meet three requirements: ? Planned increases to the LHC beam luminosity will require an overhaul of the existing Trigger system including new algorithms and system architecture. ? New algorithms will increase resource requirements; yet reducing the number of devices in the system is critical, as the need for data-sharing between devices is a primary cause of system design complexity ? As researchers use the system, they may discover they require new functionality in the Trigger. Thus the Trigger design must be flexible (reprogrammable) yet still meet tight performance constraints. Changes made to the system must result in a minimal amount of down-time. The upcoming upgrades to the LHC and its associated experiments will require a significant redesign of its triggering electronics, including the implementation of new algorithms in the Regional Calorimeter Trigger (RCT). In this thesis, I provide an analysis of historical trends in trigger systems and their implementation platforms, formulate a mathematical description of the triggering algorithms proposed for the Phase-I upgrade to the RCT for the Compact Muon Solenoid experiment at CERN?s Large Hadron Collider, describe the unique challenges of designing electronics for particle accelerators, and explore two aspects of the implementation of the RCT upgrade: (1) The algorithmic tradeoffs available and their effect on the hardware implementation cost and (2) the impact of different using existing chip partitioning schemes compared to an algorithm-aware partitioning scheme developed for the RCT. These results are analyzed for a range of modern Field-Programmable Gate Array (FPGA) implementation targets.