Novel Spiral Search Architecture for Motion Estimation
Nalamalapu, Vinod Reddy
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Hardware accelerators for motion estimation has been an active area of research over recent years. Specialized memory organizations and hardware structures are proposed to address computation intensive full search motion estimation. With the video intensive multimedia applications being deployed in embedded systems like smart phones etc., power consumption and reduced complexity are gaining importance. Existing hardware accelerators for Full search motion estimation address the computation complexity well but are not power efficient. We propose a flexible full search architecture that can start the search from any predicted search center in a given search window which is beneficial for algorithms trying to leverage the neighboring motion vector information to reduce the SAD computations. The proposed architecture also allows support for early termination algorithms based on a threshold value. In the latest H.264, if the variable block size partitioning is decided earlier based on rate-distortion performance, Our architecture can utilize the mode decision to reduce the number of SAD computations. The proposed architecture is implemented in Verilog and synthesized at 500 MHz clock speed which can easily render VGA resolution (640x480) at 60 fps. The TSMC 64nm standard cell technology library is used for synthesis.